In a computer system, a bus may be thought of as the communication interlink between various components of the computer system. Different computer systems may use different types of bus architectures. One type of bus architecture is the Industry Standard Architecture (ISA) bus. Another is the Extended ISA (EISA) bus. A more recent bus architecture is the Peripheral Component Interconnect (PCI) Local Bus architecture. As described by the PCI Local Bus Specification, Revision 2.1 (1995), the PCI Local Bus is a high performance bus that is intended as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory subsystems.
A bridge is a device or set of devices that couples one computer bus to another and allows them to communicate with each other. Generally, bridges are asymmetrical in that one bus to which a bridge is coupled will have priority over the other bus to which the bridge is also coupled. The bus with the higher priority is the one closest to the main processor of the computer system and is called the primary bus. The other bus coupled to the bridge having lower priority is called the secondary bus. Similarly, the interface of the bridge which is coupled to the primary bus is called the primary interface, while the bridge interface coupled to the secondary bus is called the secondary interface. Transactions that are forwarded from the primary interface to the secondary interface of a bridge are said to be flowing downstream while transactions forwarded from the secondary interface to the primary interface of the bridge are said to be flowing upstream.
A block diagram of a computer system is shown in FIG. 1. Host bridge 102 serves to couple processor 101 to PCI bus 104. In addition, host bridge 102 controls accesses to the main memory subsystem 103 of the computer system. There are three bus agents coupled to PCI bus 104 along with a PCI to PCI bridge 105. Bridge 105 is also coupled to PCI bus 106. There are three bus agents coupled to PCI bus 106 along with PCI to PCI bridge 107. Bridge 107 is additionally coupled to PCI bus 108. There are four bus agents coupled to PCI bus 108.
PCI buses exhibit electrical loading limitations which restrict the number of devices which can be coupled to a PCI bus. For example, the ten bus agents shown in the computer system of FIG. 1 could not all be coupled to PCI bus 104, because ten bus agents on PCI bus 104 would overload that bus. However, by creating the hierarchical structure of the computer system shown in FIG. 1 using PCI to PCI bridges 105 and 107, a system designer is afforded the ability to overcome electrical loading limits imposed by PCI buses.
Note that with respect to bridge 105, PCI bus 104 is the primary bus while PCI bus 106 is the secondary bus. Similarly, with respect to bridge 107, PCI bus 106 is the primary bus while PCI bus 108 is the secondary bus. The primary and secondary interfaces of bridge 105 are coupled to primary PCI bus 104 and secondary PCI bus 106 respectively. The primary and secondary interfaces of bridge 107 are coupled to primary PCI bus 106 and secondary PCI bus 108, respectively. Therefore, a total of four PCI interfaces exist within PCI to PCI bridges 105 and 107.
Bridges 105 and 107 allow transactions to occur between a master on one PCI bus and a target on another PCI bus. The master of a transaction that crosses a PCI to PCI bridge is said to reside on the initiating bus. The target of a transaction that crosses a PCI to PCI bridge is said to reside on the target bus. In bus architecture schemes such as PCI, multiple agents coupled to the bus must compete for ownership of the bus because only one agent can initiate a transaction at one time on the bus. The mechanism used to allow each of several agents coupled to a bus some amount of access time to that bus in a fair and rational manner is called arbitration.
For a transaction in which a bus agent coupled to PCI bus 108 is the master, while a bus agent coupled to PCI bus 104 is the target, it can take a significant amount of time for a transaction to be communicated between the master and target in the hierarchical computer system shown in FIG. 1. Through arbitration, the bus master must win ownership of PCI bus 108, PCI bus 106, and target PCI bus 104 before the transaction can be fully executed. Due to arbitration latency, bus acquisition latency, and target latency, the lower a device is in the bus hierarchy of a computer system, the more time it takes for that device to communicate with other devices closer to the processor, such as bus agents residing upstream of multiple bridges, main memory, or even the processor itself.
As a result, the PCI bus residing closest to the processor, which is coupled to the host bridge, usually supports higher performance bus agents than do PCI buses further down in the hierarchy. For example, in the computer system of FIG. 1, bus agents coupled to PCI bus 104 may include graphics devices and other data-intensive agents which require close proximity to main memory 103 and processor 101 for quick access to these units. In contrast, bus agents coupled to PCI bus 108 may include, for example, hard drives and other slower, low-performance devices.
Therefore, the hierarchical structure of the typical computer system of FIG. 1, which is implemented to overcome the loading limitations of PCI buses, limits the number of high-performance devices which can be incorporated into the system. In addition, the multiplicity of bridges necessary to create the hierarchical structure adds to the cost and increases the power consumption of the overall system. Also, for mobile computer systems, the additional space occupied by the multiple bridges increases the size of these systems.